1. Field of the Invention
Embodiments of the present invention relate to computer system memory, in particular the management of memory.
2. Related Art
In a translation-based computer system architecture, instructions can be translated from their original form into a translated form. The translation may occur in either hardware or software.
Computer systems that utilize instruction translations need to maintain instruction coherence. That is, if an instruction is translated, and then the original instruction is later modified, then it is necessary to invalidate the translated instruction as it may no longer correspond to the modified instruction. However, there may not be any correlation between the address where the translated instruction resides and the address where the original instruction resides, and so an address-based scheme is not sufficient for reliably resolving this issue.
In one prior art solution, the instruction translator maintains a set of bits referred to as translation bits, or T-bits, that correspond to physical addresses. According to this solution, a translation lookaside buffer (TLB) is modified to accommodate the T-bits, and the TLB entry insertion process is modified to add the physical address-based T-bits to the linear address-based TLB.